.. _file_format_fabric_pin_physical_location_file:

Fabric Pin Physical Location File (.xml)
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This file is generated by command :ref:`openfpga_setup_commands_write_fabric_pin_physical_location`


The fabric pin physical location file aims to show 

- Pin names of each module in an eFPGA fabric
- Preferred physical side of each pin on its module

This file is created for pin guidelines during physical design steps

An example of the file is shown as follows.

.. code-block:: xml

  <pin_location>
    <module name="sb_1__1_">
      <loc pin="chany_bottom_in[0:0]" side="bottom"/>
      <loc pin="chany_bottom_in[1:1]" side="bottom"/>
      <loc pin="chany_bottom_in[2:2]" side="bottom"/>
      <loc pin="chany_bottom_in[3:3]" side="bottom"/>
      <loc pin="chany_bottom_in[4:4]" side="bottom"/>
      <loc pin="chany_bottom_in[5:5]" side="bottom"/>
      <loc pin="chany_bottom_in[6:6]" side="bottom"/>
      <loc pin="chany_bottom_in[7:7]" side="bottom"/>
      <loc pin="chany_bottom_in[8:8]" side="bottom"/>
      <loc pin="chany_bottom_in[9:9]" side="bottom"/>
      <loc pin="chany_bottom_in[10:10]" side="bottom"/>
      <loc pin="chany_bottom_in[11:11]" side="bottom"/>
      <loc pin="chany_bottom_in[12:12]" side="bottom"/>
      <loc pin="chany_bottom_out[0:0]" side="bottom"/>
      <loc pin="chany_bottom_out[1:1]" side="bottom"/>
      <loc pin="chany_bottom_out[2:2]" side="bottom"/>
      <loc pin="chany_bottom_out[3:3]" side="bottom"/>
      <loc pin="chany_bottom_out[4:4]" side="bottom"/>
      <loc pin="chany_bottom_out[5:5]" side="bottom"/>
      <loc pin="chany_bottom_out[6:6]" side="bottom"/>
      <loc pin="chany_bottom_out[7:7]" side="bottom"/>
      <loc pin="chany_bottom_out[8:8]" side="bottom"/>
      <loc pin="chany_bottom_out[9:9]" side="bottom"/>
      <loc pin="chany_bottom_out[10:10]" side="bottom"/>
      <loc pin="chany_bottom_out[11:11]" side="bottom"/>
      <loc pin="chany_bottom_out[12:12]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0:0]" side="bottom"/>
      <loc pin="bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0:0]" side="bottom"/>
      <loc pin="chanx_left_in[0:0]" side="left"/>
      <loc pin="chanx_left_in[1:1]" side="left"/>
      <loc pin="chanx_left_in[2:2]" side="left"/>
      <loc pin="chanx_left_in[3:3]" side="left"/>
      <loc pin="chanx_left_in[4:4]" side="left"/>
      <loc pin="chanx_left_in[5:5]" side="left"/>
      <loc pin="chanx_left_in[6:6]" side="left"/>
      <loc pin="chanx_left_in[7:7]" side="left"/>
      <loc pin="chanx_left_in[8:8]" side="left"/>
      <loc pin="chanx_left_in[9:9]" side="left"/>
      <loc pin="chanx_left_in[10:10]" side="left"/>
      <loc pin="chanx_left_in[11:11]" side="left"/>
      <loc pin="chanx_left_in[12:12]" side="left"/>
      <loc pin="chanx_left_out[0:0]" side="left"/>
      <loc pin="chanx_left_out[1:1]" side="left"/>
      <loc pin="chanx_left_out[2:2]" side="left"/>
      <loc pin="chanx_left_out[3:3]" side="left"/>
      <loc pin="chanx_left_out[4:4]" side="left"/>
      <loc pin="chanx_left_out[5:5]" side="left"/>
      <loc pin="chanx_left_out[6:6]" side="left"/>
      <loc pin="chanx_left_out[7:7]" side="left"/>
      <loc pin="chanx_left_out[8:8]" side="left"/>
      <loc pin="chanx_left_out[9:9]" side="left"/>
      <loc pin="chanx_left_out[10:10]" side="left"/>
      <loc pin="chanx_left_out[11:11]" side="left"/>
      <loc pin="chanx_left_out[12:12]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_[0:0]" side="left"/>
      <loc pin="left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0:0]" side="left"/>
    </module>
  </pin_location>

.. option:: name="<string>"

  The module name in FPGA fabric, which should be a valid module defined in output Verilog netlist.

  .. note:: You should be find the exact module in the FPGA fabric if you output the Verilog netlists.

.. option:: pin="<string>"

  The name of the pin in FPGA fabric. Note that all the bus port will be flatten in this file.

  .. note:: You should be find the exact pin in the module if you output the Verilog netlists.

.. option:: side="<string>"

  The physical side of the pin should appear on the perimeter of the module.