.. _file_format_boundary_timing_template_file:

Boundary Timing Template File (.xml)
------------------------------------

This file is generated by command :ref:`openfpga_setup_commands_write_boundary_timing_template`

The boundary timing template file aims to show:

- External pin names of the eFPGA fabric
- The minimum and maximum timing values associated with each pin

This file serves as a template for generating SDC timing constraints and can be modified by users to reflect system-level timing assumptions.

An example of the file is shown as follows.

.. code-block:: xml
  <boundary_timing>
    <!The timing scale is ns-->
    <pin name="TOP_2_IN[0:0]" min="0.1" max="0.5" />
    <pin name="TOP_2_IN[2:2]" min="0.2" max="0.2" />
    <pin name="TOP_0_OUT[0:0]" min="0.3" max="0.3" />
    <pin name="TOP_0_OUT[2:2]" min="0.4" max="0.4" />
  </boundary_timing>

.. option:: pin="<string>"

  The name of the pin in FPGA fabric. Note that all the bus port will be flatten in this file

  .. note:: You should be find the exact pin in the module if you output the Verilog netlists.

.. option:: name="<string>"

  Specify the pin name of the FPGA chip

.. option:: min="<string>"

  The minimum timing value associated with this pin, expressed in nanoseconds. 

.. option:: max="<string>"

  The maximum timing value associated with this pin, expressed in nanoseconds.