Publications & References


Vaughn Betz, Jonathan Rose, and Alexander Marquardt, editors. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Norwell, MA, USA, 1999. ISBN 0792384601.


J. B. Goeders and S. J. E. Wilton. VersaPower: Power Estimation for Diverse FPGA Architectures. In 2012 International Conference on Field-Programmable Technology, 229–234. Dec 2012. doi:10.1109/FPT.2012.6412139.


Jason Luu, Jason Helge Anderson, and Jonathan Scott Rose. Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA ‘11, 227–236. New York, NY, USA, 2011. ACM. URL:, doi:10.1145/1950413.1950457.


Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, and Jason Anderson. The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA ‘12, 77–86. New York, NY, USA, 2012. ACM. URL:, doi:10.1145/2145694.2145708.


X. Tang, P. Gaillardon, and G. De Micheli. Fpga-spice: a simulation-based power estimation framework for fpgas. In 2015 33rd IEEE International Conference on Computer Design (ICCD), volume, 696–703. Oct 2015. doi:10.1109/ICCD.2015.7357183.


X. Tang, E. Giacomin, A. Alacchi, B. Chauviere, and P. Gaillardon. Openfpga: an opensource framework enabling rapid prototyping of customizable fpgas. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), volume, 367–374. Sep. 2019. doi:10.1109/FPL.2019.00065.


X. Tang, E. Giacomin, A. Alacchi, and P. Gaillardon. A study on switch block patterns for tileable fpga routing architectures. In 2019 International Conference on Field-Programmable Technology (ICFPT), volume, 247–250. 2019. doi:10.1109/ICFPT47387.2019.00039.


X. Tang, E. Giacomin, G. D. Micheli, and P. Gaillardon. FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(3):637–650, March 2019. doi:10.1109/TVLSI.2018.2883923.