OpenFPGA
latest
Overview
Why OpenFPGA?
Technical Highlights
Tutorials
Getting Started
Design Flows
Generate Fabric Netlists
From Verilog to Verification
From Verilog to GDSII
Architecture Modeling
User Manual
OpenFPGA Flow
OpenFPGA Architecture Description
OpenFPGA Shell
FPGA-SPICE
FPGA-Verilog
FPGA-Bitstream
File Formats
Utilities
Developers Manual
Version Number
Backward compatibility
CI/CD setup
Regression Tests
Tcl API
Appendix
Contact
Acknowledgement
Publications & References
OpenFPGA
<no title>
Design Flows
Edit on GitHub
Design Flows
Generate Fabric Netlists
Prepare Task Configuration File
Run OpenFPGA Task
Run icarus iVerilog Compilation
From Verilog to Verification
Netlist Generation
Run icarus iVerilog Simulation
Run Modelsim Simulation
From Verilog to GDSII
Read the Docs
v: latest
Versions
master
latest
stable
Downloads
pdf
html
epub
On Read the Docs
Project Home
Builds