OpenFPGA Architecture Description

• General Hierarchy
  • OpenFPGA Architecture Description File
  • OpenFPGA Simulation Setting File
• Additional Syntax to Original VPR XML
  • Models, Complex blocks and Physical Tiles
  • Layout
  • Switch Block
  • Routing Segments
• Configuration Protocol
  • Template
  • Configuration Chain Example
  • Frame-based Example
  • Memory bank Example
  • QuickLogic Memory bank Example
  • Standalone SRAM Example
• Direct Interconnect
  • Syntax
  • Enhanced Connection Block
  • Inter-tile Connections
• Simulation settings
  • Clock Setting
  • Simulator Option
  • Monte Carlo Simulation
  • Measurement Setting
  • Stimulus Setting
• Technology library
  • Device Library
  • Variation Library
• Circuit Library
  • Circuit Model
  • Design Technology
  • Device Technology
  • Input and Output Buffers
  • Pass Gate Logic
  • Circuit Port
  • FPGA I/O Port
• Circuit model examples
  • Inverters and Buffers
  • Pass-gate Logic
  • SRAMs
  • Logic gates
  • Multiplexers
  • Look-Up Tables
  • Datapath Flip-Flops
  • Configuration Chain Flip-Flop
  • Hard Logics
  • Routing Wire Segments
  • I/O pads
• Bind circuit modules to VPR architecture
  • Switch Blocks
  • Connection Blocks
  • Channel Wire Segments
  • Physical Tile Annotation
  • Primitive Blocks inside Multi-mode Configurable Logic Blocks
• Fabric Key
  • Key Generation
  • File Format