• Getting Started
  • How to Compile
  • OpenFPGA shortcuts
  • Supported Tools
• Design Flows
  • Generate Fabric Netlists
  • From Verilog to Verification
  • From Verilog to GDSII
• Architecture Modeling
  • A Quick Start
  • Integrating Custom Verilog Modules with user_defined_template.v
  • Build an FPGA fabric using Standard Cell Libraries
  • Creating Spypads Using XML Syntax