OpenFPGA
stable
Overview
Why OpenFPGA?
Technical Highlights
Tutorials
Getting Started
Design Flows
Architecture Modeling
User Manual
OpenFPGA Flow
OpenFPGA Architecture Description
OpenFPGA Shell
FPGA-SPICE
FPGA-Verilog
FPGA-Bitstream
File Formats
Developers Manual
CI/CD setup
Version Number
Regression Tests
Appendix
Contact
Publications & References
Frequently Asked Questions
OpenFPGA
Docs
»
<no title>
Edit on GitHub
Getting Started
How to Compile
OpenFPGA shortcuts
Supported Tools
Design Flows
Generate Fabric Netlists
From Verilog to Verification
From Verilog to GDSII
Architecture Modeling
A Quick Start
Integrating Custom Verilog Modules with user_defined_template.v
Build an FPGA fabric using Standard Cell Libraries
Creating Spypads Using XML Syntax
Read the Docs
v: stable
Versions
master
latest
stable
Downloads
pdf
html
epub
On Read the Docs
Project Home
Builds
Free document hosting provided by
Read the Docs
.