Boundary Timing Template File (.xml)

This file is generated by command write_boundary_timing_template

The boundary timing template file aims to show:

• External pin names of the eFPGA fabric

• The minimum and maximum timing values associated with each pin

This file serves as a template for generating SDC timing constraints and can be modified by users to reflect system-level timing assumptions.

An example of the file is shown as follows.

pin="<string>"

The name of the pin in FPGA fabric. Note that all the bus port will be flatten in this file

Note

You should be find the exact pin in the module if you output the Verilog netlists.

name="<string>"

Specify the pin name of the FPGA chip

min="<string>"

The minimum timing value associated with this pin, expressed in nanoseconds.

max="<string>"

The maximum timing value associated with this pin, expressed in nanoseconds.