FPGA-Verilog¶
write_fabric_verilog¶
Write the Verilog netlist for FPGA fabric based on module graph. See details in Fabric Netlists.
- --file <string> or -f <string>¶
Specify the output directory for the Verilog netlists. For example,
--file /temp/fabric_netlist/
- --default_net_type <string>¶
Specify the default net type for the Verilog netlists. Currently, supported types are
none
andwire
. Default value:none
.
- --explicit_port_mapping¶
Use explicit port mapping when writing the Verilog netlists
- --include_timing¶
Output timing information to Verilog netlists for primitive modules
- --use_relative_path¶
Force to use relative path in netlists when including other netlists. By default, this is off, which means that netlists use absolute paths when including other netlists
- --print_user_defined_template¶
Output a template Verilog netlist for all the user-defined
circuit models
in Circuit Library. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
- --no_time_stamp¶
Do not print time stamp in Verilog netlists
- --verbose¶
Show verbose log
write_full_testbench¶
Write the full testbench for FPGA fabric in Verilog format. See details in Testbench.
- --file <string> or -f <string>¶
The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example,
--file /temp/testbench
- --bitstream <string>¶
The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in Plain text (.bit)). For example,
--bitstream and2.bit
- --fabric_netlist_file_path <string>¶
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example,
--file /temp/fabric/fabric_netlists.v
- --reference_benchmark_file_path <string>¶
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example,
--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v
Note
If not specified, the testbench will not include any self-checking feature!
- --pin_constraints_file <string> or -pcf <string>¶
Specify the Pin Constraints File (PCF) if you want to custom stimulus in testbenches. For example,
-pin_constraints_file pin_constraints.xml
Strongly recommend for multi-clock simulations. See detailed file format about Pin Constraints File (.xml).
- --bus_group_file <string> or -bgf <string>¶
Specify the Bus Group File (BGF) if you want to group pins to buses. For example,
-bgf bus_group.xml
Strongly recommend when input HDL contains bus ports. See detailed file format about Bus Group File (.xml).
- --fast_configuration¶
Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
Note
If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
- --explicit_port_mapping¶
Use explicit port mapping when writing the Verilog netlists
- --default_net_type <string>¶
Specify the default net type for the Verilog netlists. Currently, supported types are
none
andwire
. Default value:none
.
- --include_signal_init¶
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
Note
We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
Warning
Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- --no_time_stamp¶
Do not print time stamp in Verilog netlists
- --use_relative_path¶
Force to use relative path in netlists when including other netlists. By default, this is off, which means that netlists use absolute paths when including other netlists
- --verbose¶
Show verbose log
write_preconfigured_fabric_wrapper¶
Write the Verilog wrapper for a preconfigured FPGA fabric. See details in Testbench.
- --file <string> or -f <string>¶
The output directory for the netlists. We suggest the use of same output directory as fabric Verilog netlists. For example,
--file /temp/testbench
- --fabric_netlist_file_path <string>¶
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example,
--file /temp/fabric/fabric_netlists.v
- --pin_constraints_file <string> or -pcf <string>¶
Specify the Pin Constraints File (PCF) if you want to custom stimulus in testbenches. For example,
-pin_constraints_file pin_constraints.xml
Strongly recommend for multi-clock simulations. See detailed file format about Pin Constraints File (.xml).
- --bus_group_file <string> or -bgf <string>¶
Specify the Bus Group File (BGF) if you want to group pins to buses. For example,
-bgf bus_group.xml
Strongly recommend when input HDL contains bus ports. See detailed file format about Bus Group File (.xml).
- --explicit_port_mapping¶
Use explicit port mapping when writing the Verilog netlists
- --default_net_type <string>¶
Specify the default net type for the Verilog netlists. Currently, supported types are
none
andwire
. Default value:none
.
- --embed_bitstream <string>¶
Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are
none
,iverilog
andmodelsim
. Default value:modelsim
.Warning
If the option
none
is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!Warning
Please specify
iverilog
if you are using icarus iVerilog simulator.
- --include_signal_init¶
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
Note
We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
Warning
Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- --no_time_stamp¶
Do not print time stamp in Verilog netlists
- --verbose¶
Show verbose log
write_preconfigured_testbench¶
Write the Verilog testbench for a preconfigured FPGA fabric. See details in Testbench.
- --file <string> or -f <string>¶
The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example,
--file /temp/testbench
- --fabric_netlist_file_path <string>¶
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example,
--file /temp/fabric/fabric_netlists.v
- --reference_benchmark_file_path <string>¶
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example,
--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v
Note
If not specified, the testbench will not include any self-checking feature!
- --pin_constraints_file <string> or -pcf <string>¶
Specify the Pin Constraints File (PCF) if you want to custom stimulus in testbenches. For example,
-pin_constraints_file pin_constraints.xml
Strongly recommend for multi-clock simulations. See detailed file format about Pin Constraints File (.xml).
- --bus_group_file <string> or -bgf <string>¶
Specify the Bus Group File (BGF) if you want to group pins to buses. For example,
-bgf bus_group.xml
Strongly recommend when input HDL contains bus ports. See detailed file format about Bus Group File (.xml).
- --explicit_port_mapping¶
Use explicit port mapping when writing the Verilog netlists
- --default_net_type <string>¶
Specify the default net type for the Verilog netlists. Currently, supported types are
none
andwire
. Default value:none
.
- --no_time_stamp¶
Do not print time stamp in Verilog netlists
- --use_relative_path¶
Force to use relative path in netlists when including other netlists. By default, this is off, which means that netlists use absolute paths when including other netlists
- --verbose¶
Show verbose log
write_simulation_task_info¶
Write an interchangeable file in
.ini
format to interface HDL simulators, such as iVerilog and Modelsim.
- --file <string> or -f <string>¶
Specify the file path to output simulation-related information. For example,
--file simulation.ini
- --hdl_dir <string>¶
Specify the directory path where HDL netlists are created. For example,
--hdl_dir ./SRC
- --reference_benchmark_file_path <string>¶
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example,
--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v
- --testbench_type <string>¶
Specify the type of testbenches [
preconfigured_testbench``|``full_testbench
]. By default, it is thepreconfigured_testbench
.
- --time_unit <string>¶
Specify a time unit to be used in SDC files. Acceptable values are string:
as
|fs
|ps
|ns
|us
|ms
|ks
|Ms
. By default, we will consider second (ms
).
- --verbose¶
Show verbose log