Welcome to OpenFPGA’s documentation!

Overview

• Why OpenFPGA?
  • Fully Customizable Architecture
  • FPGA-Verilog
  • FPGA-SDC
  • FPGA-Bitstream
  • FPGA-SPICE
• Technical Highlights
  • Supported Circuit Designs
  • Supported FPGA Architectures
  • Supported Verilog Modeling

Tutorials

• Getting Started
  • How to Compile
  • OpenFPGA Shell Commands
  • Supported Tools
• Design Flows
  • Generate Fabric Netlists
  • From Verilog to Verification
  • From Verilog to GDSII
• Architecture Modeling
  • A Quick Start
  • Integrating Custom Verilog Modules with user_defined_template.v
  • Build an FPGA fabric using Standard Cell Libraries
  • Creating Spypads Using XML Syntax

User Manual

• OpenFPGA Flow
  • OpenFPGA Flow
  • OpenFPGA Task
• OpenFPGA Architecture Description
  • General Hierarchy
  • Additional Syntax to Original VPR XML
  • Configuration Protocol
  • Inter-Tile Direct Interconnection extensions
  • Simulation settings
  • Technology library
  • Circuit Library
  • Circuit model examples
  • Bind circuit modules to VPR architecture
  • Fabric Key
• OpenFPGA Shell
  • Launch OpenFPGA Shell
  • OpenFPGA Script Format
  • Commands
• FPGA-SPICE
  • Command-line Options
  • Hierarchy of SPICE Output Files
  • Run SPICE simulation
  • Create Customized SPICE Modules
• FPGA-Verilog
  • Fabric Netlists
  • Testbench
• FPGA-Bitstream
  • Generic Bitstream
  • Fabric-dependent Bitstream
• File Formats
  • Pin Constraints File (.xml)
  • Repack Design Constraints (.xml)
  • Architecture Bitstream (.xml)
  • Fabric-dependent Bitstream
  • Bitstream Setting (.xml)
  • Fabric Key (.xml)
  • I/O Mapping File (.xml)
  • I/O Information File (.xml)
  • Bitstream Distribution File (.xml)
  • Bus Group File (.xml)
  • Pin Constraints File (.pcf)
  • Pin Table File (.csv)

Developers Manual

• Version Number
  • Convention
  • Version Update Rules
• Backward compatibility
  • OpenFPGA v1.1
• CI/CD setup
  • How to debug failed regression test
  • Release Docker Images
  • CI after cloning repository
• Regression Tests
  • Run a Test
  • Test Options
• Tcl API

Appendix

• Contact
• Acknowledgement
• Publications & References

For more information on the VTR see vtr_doc or vtr_github

For more information on the Yosys see yosys_doc or yosys_github

For more information on the original FPGA architecture description language see xml_vtr

Indices and tables

• Index

• Module Index

• Search Page