OpenFPGA
master

Overview

  • Why OpenFPGA?
  • Technical Highlights

Tutorials

  • Getting Started
  • Design Flows
  • Architecture Modeling

User Manual

  • OpenFPGA Flow
  • OpenFPGA Architecture Description
  • OpenFPGA Shell
  • FPGA-SPICE
  • FPGA-Verilog
    • Fabric Netlists
    • Testbench
  • FPGA-Bitstream
  • File Formats

Developers Manual

  • Version Number
  • Backward compatibility
  • CI/CD setup
  • Regression Tests
  • Tcl API

Appendix

  • Contact
  • Acknowledgement
  • Publications & References
OpenFPGA
  • Docs »
  • <no title> »
  • FPGA-Verilog
  • Edit on GitHub

FPGA-VerilogΒΆ

  • Fabric Netlists
    • Top-level Netlists
    • Logic Blocks
    • Routing Blocks
    • Primitive Modules
  • Testbench
    • Full Testbench
    • Formal-oriented Testbench
    • General Usage
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© Copyright 2018, Xifan Tang Revision a3319bf5.

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