OpenFPGA
Overview
Why OpenFPGA?
Technical Highlights
Tutorials
Getting Started
Design Flows
Generate Fabric Netlists
From Verilog to Verification
From Verilog to GDSII
Architecture Modeling
User Manual
OpenFPGA Flow
OpenFPGA Architecture Description
OpenFPGA Shell
FPGA-SPICE
FPGA-Verilog
FPGA-Bitstream
File Formats
Utilities
Developers Manual
Version Number
Backward compatibility
Continous Integration
Regression Tests
Tcl API
Contributor Guidelines
Appendix
Contact
Acknowledgement
Publications & References
OpenFPGA
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Design Flows
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Design Flows
Generate Fabric Netlists
Prepare Task Configuration File
Run OpenFPGA Task
Run icarus iVerilog Compilation
From Verilog to Verification
Netlist Generation
Run icarus iVerilog Simulation
Run Modelsim Simulation
From Verilog to GDSII