OpenFPGA
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Overview

  • Why OpenFPGA?
  • Technical Highlights

Tutorials

  • Getting Started
  • Design Flows
  • Architecture Modeling

User Manual

  • OpenFPGA Flow
  • OpenFPGA Architecture Description
    • General Hierarchy
    • Additional Syntax to Original VPR XML
    • Configuration Protocol
    • Inter-Tile Direct Interconnection extensions
    • Simulation settings
    • Technology library
    • Circuit Library
    • Circuit model examples
    • Bind circuit modules to VPR architecture
    • Fabric Key
  • OpenFPGA Shell
  • FPGA-SPICE
  • FPGA-Verilog
  • FPGA-Bitstream
  • File Formats

Developers Manual

  • Version Number
  • Backward compatibility
  • CI/CD setup
  • Regression Tests
  • Tcl API

Appendix

  • Contact
  • Acknowledgement
  • Publications & References
OpenFPGA
  • Docs »
  • <no title> »
  • OpenFPGA Architecture Description
  • Edit on GitHub

OpenFPGA Architecture DescriptionΒΆ

  • General Hierarchy
    • OpenFPGA Architecture Description File
    • OpenFPGA Simulation Setting File
  • Additional Syntax to Original VPR XML
    • Models, Complex blocks and Physical Tiles
    • Layout
    • Switch Block
    • Routing Segments
  • Configuration Protocol
    • Template
    • Configuration Chain Example
    • Frame-based Example
    • Memory bank Example
    • QuickLogic Memory bank Example
    • Standalone SRAM Example
  • Inter-Tile Direct Interconnection extensions
    • Directlist
    • Example
    • Truth table
  • Simulation settings
    • Clock Setting
    • Simulator Option
    • Monte Carlo Simulation
    • Measurement Setting
    • Stimulus Setting
  • Technology library
    • Device Library
    • Variation Library
  • Circuit Library
    • Circuit Model
    • Design Technology
    • Device Technology
    • Input and Output Buffers
    • Pass Gate Logic
    • Circuit Port
    • FPGA I/O Port
  • Circuit model examples
    • Inverters and Buffers
    • Pass-gate Logic
    • SRAMs
    • Logic gates
    • Multiplexers
    • Look-Up Tables
    • Datapath Flip-Flops
    • Configuration Chain Flip-Flop
    • Hard Logics
    • Routing Wire Segments
    • I/O pads
  • Bind circuit modules to VPR architecture
    • Switch Blocks
    • Connection Blocks
    • Channel Wire Segments
    • Physical Tile Annotation
    • Primitive Blocks inside Multi-mode Configurable Logic Blocks
  • Fabric Key
    • Key Generation
    • File Format
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