OpenFPGA
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Overview

  • Why OpenFPGA?
  • Technical Highlights

Tutorials

  • Getting Started
  • Design Flows
  • Architecture Modeling
    • A Quick Start
    • Integrating Custom Verilog Modules with user_defined_template.v
    • Build an FPGA fabric using Standard Cell Libraries
    • Creating Spypads Using XML Syntax

User Manual

  • OpenFPGA Flow
  • OpenFPGA Architecture Description
  • OpenFPGA Shell
  • FPGA-SPICE
  • FPGA-Verilog
  • FPGA-Bitstream
  • File Formats

Developers Manual

  • Version Number
  • Backward compatibility
  • CI/CD setup
  • Regression Tests
  • Tcl API

Appendix

  • Contact
  • Acknowledgement
  • Publications & References
OpenFPGA
  • Docs »
  • <no title> »
  • Architecture Modeling
  • Edit on GitHub

Architecture ModelingΒΆ

  • A Quick Start
    • Adapt VPR Architecture
    • Craft OpenFPGA Architecture
    • Simulation Settings
  • Integrating Custom Verilog Modules with user_defined_template.v
    • Introduction and Setup
    • Motivation
    • Fixing the Error
    • Fixing the Error with user_defined_template.v
  • Build an FPGA fabric using Standard Cell Libraries
    • Introduction
    • Create and Verify the OpenFPGA Circuit Model
    • Clone Skywater PDK into OpenFPGA
    • Create and Verify the Standard Cell Library Circuit Model
  • Creating Spypads Using XML Syntax
    • Introduction
    • Pre-Built Spypads
    • Building Spypads
    • Conclusion
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