• OpenFPGA Flow
  • OpenFPGA Flow
  • OpenFPGA Task
• OpenFPGA Architecture Description
  • General Hierarchy
  • Additional Syntax to Original VPR XML
  • Configuration Protocol
  • Inter-Tile Direct Interconnection extensions
  • Simulation settings
  • Technology library
  • Circuit Library
  • Circuit model examples
  • Bind circuit modules to VPR architecture
  • Fabric Key
• OpenFPGA Shell
  • Launch OpenFPGA Shell
  • OpenFPGA Script Format
  • Commands
• FPGA-SPICE
  • Command-line Options
  • Hierarchy of SPICE Output Files
  • Run SPICE simulation
  • Create Customized SPICE Modules
• FPGA-Verilog
  • Fabric Netlists
  • Testbench
• FPGA-Bitstream
  • Generic Bitstream
  • Fabric-dependent Bitstream
• File Formats
  • Pin Constraints File (.xml)
  • Repack Design Constraints (.xml)
  • Architecture Bitstream (.xml)
  • Fabric-dependent Bitstream
  • Bitstream Setting (.xml)
  • Fabric Key (.xml)
  • I/O Mapping File (.xml)
  • I/O Information File (.xml)
  • Bitstream Distribution File (.xml)
  • Bus Group File (.xml)
  • Pin Constraints File (.pcf)
  • Pin Table File (.csv)