Technical Highlights
The following lists of technical features were created to help users find their needs for customizing FPGA fabrics.(as of February 2021)
Supported Circuit Designs
Circuit Types
|
Auto-
generation
|
User-
Defined
|
Design Topologies
|
---|---|---|---|
Inverter |
Yes |
Yes |
|
Buffer |
Yes |
Yes |
|
AND gate |
Yes |
Yes |
|
OR gate |
Yes |
Yes |
|
MUX2 gate |
Yes |
Yes |
|
Pass gate |
Yes |
Yes |
|
Look-Up Table |
Yes |
Yes |
|
Routing
Multiplexer
|
Yes |
No |
|
Configurable
Memory
|
No |
Yes |
|
Data Memory |
No |
Yes |
|
Arithmetic
Units
|
No |
Yes |
|
I/O |
No |
Yes |
|
The user defined netlist could come from a standard cell. See Build an FPGA fabric using Standard Cell Libraries for details.
Supported FPGA Architectures
We support most FPGA architectures that VPR can support! The following are the most commonly seen architectural features:
Block Type |
Architecture features |
---|---|
Programmable Block |
|
Routing Block |
|
|
Supported Verilog Modeling
OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs
Synthesizable Behavioral Verilog
Structural Verilog
Implicit/Explicit port mapping