OpenFPGA

Overview

  • Why OpenFPGA?
  • Technical Highlights

Tutorials

  • Getting Started
  • Design Flows
  • Architecture Modeling

User Manual

  • OpenFPGA Flow
  • OpenFPGA Architecture Description
  • OpenFPGA Shell
  • FPGA-SPICE
  • FPGA-Verilog
  • FPGA-Bitstream
  • File Formats
    • Pin Constraints File (.xml)
    • Repack Design Constraints (.xml)
    • Architecture Bitstream (.xml)
    • Fabric-dependent Bitstream
    • Bitstream Setting (.xml)
    • Fabric Key (.xml)
    • I/O Mapping File (.xml)
    • I/O Information File (.xml)
    • Bitstream Distribution File (.xml)
    • Bus Group File (.xml)
    • Pin Constraints File (.pcf)
    • Pin Table File (.csv)
    • Clock Network (.xml)
    • Fabric I/O Naming (.xml)
    • Fabric Module Naming (.xml)
    • Tile Organization (.xml)
    • Fabric Pin Physical Location File (.xml)
    • Fabric Hierarchy File (.yaml)
    • Reference File (.yaml)
    • Unique Blocks (.xml)
  • Utilities

Developers Manual

  • Version Number
  • Backward compatibility
  • Continous Integration
  • Regression Tests
  • Tcl API
  • Contributor Guidelines

Appendix

  • Contact
  • Acknowledgement
  • Publications & References
OpenFPGA
  • <no title>
  • File Formats
  • View page source

File Formats

OpenFPGA widely uses XML format for interchangeable files

  • Pin Constraints File (.xml)
  • Repack Design Constraints (.xml)
    • Pin constraint
    • Ignore net
  • Architecture Bitstream (.xml)
  • Fabric-dependent Bitstream
    • Plain text (.bit)
    • XML (.xml)
  • Bitstream Setting (.xml)
    • pb_type-related Settings
    • Default Mode Bits-related Settings
    • Interconnection-related Settings
    • Clock Routing-related Settings
    • non_fabric-related Settings
    • overwrite_bitstream-related Settings
  • Fabric Key (.xml)
    • Configurable Module
    • Configurable Region
    • Configurable Block
    • BL Shift Register Banks
    • WL Shift Register Banks
  • I/O Mapping File (.xml)
  • I/O Information File (.xml)
  • Bitstream Distribution File (.xml)
    • Region-Level Bitstream Distribution
    • Block-Level Bitstream Distribution
  • Bus Group File (.xml)
    • Bus-related Syntax
    • Pin-related Syntax
  • Pin Constraints File (.pcf)
  • Pin Table File (.csv)
  • Clock Network (.xml)
    • General Settings
    • Clock Network Settings
    • Clock Spine Settings
    • Intermediate Driver
    • Switch Point Settings
    • Tap Point Settings
  • Fabric I/O Naming (.xml)
    • Syntax
    • Example
  • Fabric Module Naming (.xml)
    • Syntax
  • Tile Organization (.xml)
    • Syntax
  • Fabric Pin Physical Location File (.xml)
  • Fabric Hierarchy File (.yaml)
  • Reference File (.yaml)
  • Unique Blocks (.xml)
    • Configurable Block
    • Configurable Instance
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© Copyright 2018, Xifan Tang.

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