OpenFPGA
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Overview
Why OpenFPGA?
Technical Highlights
Tutorials
Getting Started
Design Flows
Architecture Modeling
User Manual
OpenFPGA Flow
OpenFPGA Architecture Description
OpenFPGA Shell
FPGA-SPICE
FPGA-Verilog
FPGA-Bitstream
File Formats
Utilities
Developers Manual
Version Number
Backward compatibility
CI/CD setup
Regression Tests
Tcl API
Appendix
Contact
Acknowledgement
Publications & References
OpenFPGA
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Getting Started
How to Compile
OpenFPGA Shell Commands
Supported Tools
Design Flows
Generate Fabric Netlists
From Verilog to Verification
From Verilog to GDSII
Architecture Modeling
A Quick Start
Integrating Custom Verilog Modules with user_defined_template.v
Build an FPGA fabric using Standard Cell Libraries
Creating Spypads Using XML Syntax
Read the Docs
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