Supported Tools

Internal Tools

To enable various design purposes, OpenFPGA integrates several tools to i.e., FPGA-Verilog, FPGA-SDC and FPGA-bitstream (highlighted green in OpenFPGA tool suites and design flows, with other popular open-source EDA tools, i.e., VPR and Yosys.

map to buried treasure

Fig. 6 OpenFPGA tool suites and design flows

Third-Party Tools

OpenFPGA accepts and outputs in standard file formats, and therefore can interface a wide range of commercial and open-source tools.



Version Requirement


Synopsys IC Compiler II

Cadence Innovus

v2019.03 or later

v19.1 or later

Timing Analyzer

Synopsys PrimeTime

Cadence Tempus

v2019.03 or later

v19.15 or later


Synopsys VCS

Synopsys Formality

Mentor ModelSim

Mentor QuestaSim

Cadence NCSim

Icarus iVerilog

v2019.06 or later

v2019.03 or later

v10.6 or later

v2019.3 or later

v15.2 or later

v10.1 or later

  • The version requirements is based on our local tests. Older versions may work.