Module Rename Assistant
Module Rename Assistant is a tool to help users to craft module name files (see details in file_formats_module_naming_files).
This tool is useful to adapt module naming from a fabric to another, considering the two fabrics share the same building blocks, i.e., tile, routing blocks etc.
For example, when engineers craft a module naming file for a fabric A
, and would like to migrate the module naming rules for anthor fabric B
, module naming rules have to be adapted due to the changes on default names of building blocks.
The tool can be found at /build/libs/libnamemanager/module_rename_assistant
The tool includes the following options:
- --reference_fabricA_names <string>
Specifiy a reference module name file for fabric A. This is typically generated by OpenFPGA through the commmand write_module_naming_rules. The reference fabric key file is treated as the baseline, on which the renamed module file will be compared to.
- --renamed_fabricA_names <string>
Specify the hand-crafted module name file for fabric A, which is typically hand-crafted by users.
- --reference_fabricB_names <string>
Specifiy a reference module name file for fabric B. This is typically generated by OpenFPGA through the commmand write_module_naming_rules. The reference fabric key file is treated as the baseline, on which the renamed module file will be compared to.
- --output <string>
Specify the renamed module name file for fabric B to be outputted. For example, the fabric A contains reference names:
<module_name default="tile_1__1_" given="tile_4_"/>
while the renamed module for fabric A includes:
<module_name default="tile_1__1_" given="tile_big"/>
the fabric B shares the same given name tile_4_
but in a different default name.
<module_name default="tile_2__2_" given="tile_4_"/>
the resulting output renamed module file includes:
<module_name default="tile_2__2_" given="tile_big"/>
- --verbose
To enable verbose output
- --help
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