Build the routing resource graph based on an defined programmable clock network, and append it to the existing routing resource graph built by VPR.
Use command openfpga_setup_command_read_openfpga_clock_arch` to load the clock network.
Route clock signals on the built routing resource graph which contains a programmable clock network.
Clock signals will be auto-detected and routed based on pin constraints which are provided by users.
Specify the Pin Constraints File (PCF) when the clock network contains multiple clock pins. For example, -pin_constraints_filepin_constraints.xml
Strongly recommend for multi-clock network. See detailed file format about Pin Constraints File (.xml).
Specify the signal activity file. For example, --activity_filecounter.act.
This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at Simulation settings.
Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.
Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ,.
When specified, only the GSBs whose names match the list will be outputted to files.
If not specified, all the GSBs will be outputted.
Note
When option --unique is enable, the given name of GSBs should match the unique modules!
Check and correct any naming conflicts in the BLIF netlist
This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
Warning
This command may be deprecated in future when it is merged to VPR upstream
Apply fix-up to clustering nets based on routing results
Note
Suggest to skip the similar fix-up applied by VPR through options --skip_sync_clustering_and_routing_resultson when calling vpr in openfpga shell.
Warning
This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for Look-Up Tables (LUTs) but you want to enable logic equivalent for input pins of LUTs
Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
Group fine-grained programmable blocks, connection blocks and switch blocks into tiles. Once enabled, tiles will be added to the top-level module. Otherwise, the top-level module consists of programmable blocks, connection blocks and switch blocks. The tile style can be customized through a file. See details in Tile Organization (.xml). When enabled, the Verilog netlists will contain additional netlists that model tiles (see details in Tiles).
Warning
This option does not support --duplicate_grid_pin!
Warning
This option requires --compress_routing to be enabled!
Group configuration memory blocks under each CLB/SB/CB etc. into a centralized configuration memory blocks, as depicted in Fig. 67. When disabled, the configuration memory blocks are placed in a distributed way under CLB/SB/CB etc. For example, each programming resource, e.g., LUT, has a dedicated configuration memory block, being placed in the same module. When enabled, as illustrated in Fig. 68, the physical memory block locates under a CLB, driving a number of logical memory blocks which are close to the programmable resources. The logical memory blocks contain only pass-through wires which can be optimized out during physical design phase.
Fig. 67 Impact on grouping configuable blocks: before and after
Fig. 68 Netlist hierarchy on grouped configuable blocks
Use index in module names, e.g., cbx_2_. This is applied to routing modules, as well as tile modules when option --group_tile is enabled. If disabled, the module name consist of coordinates, e.g., cbx_1__2_.
Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
Warning
Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
Output current fabric key to an XML file. For example, write_fabric_key--filefpga_2x2.xml See details in Fabric Key (.xml).
Note
This command can output module-level keys while the --write_fabric_key option in command build_fabric does NOT support! Strongly recommend to use this command to obtain fabric key.
Add a wrapper module fpga_core as an intermediate layer to FPGA fabric. After this command, the existing module fpga_top will remain the top-level module while there is a new module fpga_core under it. Under fpga_core, there will be the detailed building blocks.
This is optional. Specify the I/O naming rules when connecting I/Os of fpga_core module to the top-level module fpga_top. If not defined, the fpga_top will be the same as fpga_core w.r.t. ports. See details about the file format of I/O naming rules in Fabric I/O Naming (.xml).
This is optional. Specify the instance name to be used when instanciate the fpga_core module under the top-level module fpga_top. If not defined, by default it is fpga_core_inst.
Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
Warning
Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [explicit``|``quicklogic]. When explicit is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in Pin Table File (.csv)). When quicklogic is selected, pin direction is inferred by port name: a port whose postfix is _A2F is an input, while a port whose postfix is _A2F is an output. By default, it is explicit.
Specify the name of modules to be considered. Support regular expression, e.g., tile*. When provided, only pins of selected modules will be outputted. By default, a wildcard * is considered, which means all the modules will be considered.
