Setup OpenFPGA

read_openfpga_arch

Read the XML file about architecture description (see details in General Hierarchy)

--file <string> or -f <string>

Specify the file name. For example, --file openfpga_arch.xml

--verbose

Show verbose log

write_openfpga_arch

Write the OpenFPGA XML architecture file to a file

--file <string> or -f <string>

Specify the file name. For example, --file arch_echo.xml

--verbose

Show verbose log

read_openfpga_simulation_setting

Read the XML file about simulation settings (see details in Simulation settings)

--file <string> or -f <string>

Specify the file name. For example, --file auto_simulation_setting.xml

--verbose

Show verbose log

write_openfpga_simulation_setting

Write the OpenFPGA XML simulation settings to a file

--file <string> or -f <string>

Specify the file name. For example, --file auto_simulation_setting_echo.xml. See details about file format at Simulation settings.

--verbose

Show verbose log

read_openfpga_bitstream_setting

Read the XML file about bitstream settings (see details in Bitstream Setting (.xml))

--file <string> or -f <string>

Specify the file name. For example, --file bitstream_setting.xml

--verbose

Show verbose log

write_openfpga_bitstream_setting

Write the OpenFPGA XML bitstream settings to a file

--file <string> or -f <string>

Specify the file name. For example, --file auto_bitstream_setting_echo.xml. See details about file format at Bitstream Setting (.xml).

--verbose

Show verbose log

link_openfpga_arch

Annotate the OpenFPGA architecture to VPR data base

--activity_file <string>

Specify the signal activity file. For example, --activity_file counter.act. This is required when users wants OpenFPGA to automatically find the number of clocks in simulations. See details at Simulation settings.

--sort_gsb_chan_node_in_edges

Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules

--verbose

Show verbose log

write_gsb_to_xml

Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files

--file <string> or -f <string>

Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file For example, --file /temp/gsb_output

--unique

Only output unique GSBs to XML files

--exclude_rr_info

Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.

--exclude <string>

Exclude part of the GSB data to be outputted. Can be [sb``|``cbx``|``cby]. Users can exclude multiple parts by using a splitter ,. For example,

• --exclude sb

• --exclude sb,cbx

--gsb_names <string>

Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ,. When specified, only the GSBs whose names match the list will be outputted to files. If not specified, all the GSBs will be outputted.

Note

When option --unique is enable, the given name of GSBs should match the unique modules!

For example,

• --gsb_names gsb_2__4_,gsb_3__2_

• --gsb_names gsb_2__4_

--verbose

Show verbose log

Note

This command is used to help users to study the difference between GSBs

check_netlist_naming_conflict

Check and correct any naming conflicts in the BLIF netlist This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.

Warning

This command may be deprecated in future when it is merged to VPR upstream

--fix

Apply fix-up to the names that violate the syntax

--report <string>

Report the naming fix-up to an XML-based log file. For example, --report rename.xml

pb_pin_fixup

Apply fix-up to clustering nets based on routing results

Note

Suggest to skip the similar fix-up applied by VPR through options --skip_sync_clustering_and_routing_results on when calling vpr in openfpga shell.

Warning

This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for Look-Up Tables (LUTs) but you want to enable logic equivalent for input pins of LUTs

Warning

This command may be deprecated in future

--verbose

Show verbose log

lut_truth_table_fixup

Apply fix-up to Look-Up Table truth tables based on packing results

Warning

This command may be deprecated in future when it is merged to VPR upstream

--verbose

Show verbose log

build_fabric

Build the module graph.

--compress_routing

Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.

--duplicate_grid_pin

Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed

--load_fabric_key <string>

Load an external fabric key from an XML file. For example, --load_fabric_key fpga_2x2.xml See details in Fabric Key (.xml).

--generate_random_fabric_key

Generate a fabric key in a random way

--write_fabric_key <string>.

Output current fabric key to an XML file. For example, --write_fabric_key fpga_2x2.xml See details in Fabric Key (.xml).

--frame_view

Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.

Warning

Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!

--verbose

Show verbose log

Note

This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE

write_fabric_hierarchy

Write the hierarchy of FPGA fabric graph to a plain-text file

--file <string> or -f <string>

Specify the file name to write the hierarchy.

--depth <int>

Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.

--verbose

Show verbose log

Note

This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).

write_fabric_io_info

Write the I/O information of FPGA fabric to an XML file

--file <string> or -f <string>

Specify the file name to write the I/O information

--no_time_stamp

Do not print time stamp in bitstream files

--verbose

Show verbose log

Note

This file is designed for pin constraint file conversion.

pcf2place

Convert a Pin Constraint File (.pcf, see details in Pin Constraints File (.pcf)) to a placement file)

--pcf <string>

Specify the path to the users’ pin constraint file

--blif <string>

Specify the path to the users’ post-synthesis netlist

--fpga_io_map <string>

Specify the path to the FPGA I/O location. Achieved by the command write_fabric_io_info

--pin_table <string>

Specify the path to the pin table file, which describes the pin mapping between chip I/Os and FPGA I/Os. See details in Pin Table File (.csv)

--fpga_fix_pins <string>

Specify the path to the placement file which will be outputted by running this command

--pin_table_direction_convention <string>

Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [explicit``|``quicklogic]. When explicit is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in Pin Table File (.csv)). When quicklogic is selected, pin direction is inferred by port name: a port whose postfix is _A2F is an input, while a port whose postfix is _A2F is an output. By default, it is explicit.

--no_time_stamp

Do not print time stamp in bitstream files

--verbose

Show verbose log