Tile Organization (.xml)

The XML-based description language is used to describe how each tile is composed. For example, what programmable blocks, connection blocks and switch blocks should be included.

Using the description language, users can customize the tiles of an FPGA fabric, as detailed as each component in each tile.

Under the root node <tiles>, the detailes of tile organization can be described.

<tiles style="<string>"/>


Detailed syntax are presented as follows.


Specify the style of tile organization. Can be [top_left | top_right | bottom_left | bottom_right | custom]


Currently, only top_left is supported!

The top_left is a shortcut to define the organization for all the tiles. Fig. 77 shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.

An example of top-left style of tile

Fig. 77 An example of top-left style of a tile in FPGA fabric