Bitstream Setting (.xml)¶
An example of bitstream settings is shown as follows. This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics.
Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users’s responsibility to ensure correct bitstream.
<openfpga_bitstream_setting> <pb_type name="<string>" source="eblif" content=".param LUT" is_mode_select_bistream="true" bitstream_offset="1"/> <interconnect name="<string>" default_path="<string>"/> </openfpga_bitstream_setting>