Bus Group File (.xml)

The bus group file aims to show

  • How bus ports are flatten by EDA engines, e.g., synthesis.

  • What are the pins in post-routing corresponding to the bus ports before synthesis

An example of file is shown as follows.

  <bus name="i_addr[0:3]" big_endian="false">
    <pin id="0" name="i_addr_0_"/>
    <pin id="1" name="i_addr_1_"/>
    <pin id="2" name="i_addr_2_"/>
    <pin id="3" name="i_addr_3_"/>