Fabric Hierarchy File (.yaml)
This file is generated by command write_fabric_hierarchy
The fabric hierarchy file aims to show module trees of a number of given roots
This file is created for netlist manipulation and detailed floorplanning during physical design steps
By using the options of the command write_fabric_hierarchy, user can selectively output the module tree on their needs.
An example of the file is shown as follows.
fpga_top:
tile_0__2_:
sb_0__1_:
mux_tree_tapbuf_size2:
INVTX1
const1
tap_buf4
mux_tree_tapbuf_basis_input2_mem1:
- TGATE
mux_tree_tapbuf_size2_feedthrough_mem
sb_1__config_group_mem_size40:
mux_tree_tapbuf_size2_mem:
- DFF
tile_1__2_:
grid_io_top:
logical_tile_io_mode_io_:
logical_tile_io_mode_physical__iopad:
- GPIO
- GPIO_feedthrough_DFF_mem
direct_interc
In this example, the root module is fpga_top
.
The child modules under fpga_top
are tile_0__2_
and tile_1__2_
.
Note that the leaf nodes are shown as a list, e.g., GPIO
and GPIO_feedthrough_DFF_mem
.
When multiple root modules are defined, the output could be
sb_0__1_:
- mux_tree_tapbuf_size2
sb_1__0_:
- mux_tree_tapbuf_size2
sb_1__1_:
- mux_tree_tapbuf_size2
cbx_1__0_:
- mux_tree_tapbuf_size4
cbx_1__1_:
- mux_tree_tapbuf_size4
cby_0__1_:
- mux_tree_tapbuf_size2
- mux_tree_tapbuf_size4
cby_1__1_:
- mux_tree_tapbuf_size4