Index

Symbols

--activity_file command line option run_fpga_flow.py command line option --base_verilog run_fpga_flow.py command line option --batch_execution command line option --batch_mode command line option --bitstream command line option --black_box_ace run_fpga_flow.py command line option --blif command line option --bus_group_file command line option, [1], [2], [3] --command command line option --command_stream command line option --compress_routing command line option --constrain_cb command line option --constrain_configurable_memory_outputs command line option --constrain_global_port command line option --constrain_grid command line option --constrain_non_clock_global_port command line option --constrain_routing_multiplexer_outputs command line option --constrain_sb command line option --constrain_switch_block_outputs command line option --constrain_zero_delay_paths command line option --debug command line option, [1] run_fpga_flow.py command line option --default_net_type command line option, [1], [2], [3], [4] --depth command line option, [1] --design_constraints command line option --duplicate_grid_pin command line option --dut_module command line option, [1] --embed_bitstream command line option --exclude command line option --exclude_rr_info command line option --exit_on_fail command line option --explicit_port_mapping command line option, [1], [2], [3], [4] --fabric_netlist_file_path command line option, [1], [2] --fast_configuration command line option, [1] --file command line option, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27] --fix command line option --fix_route_chan_width run_fpga_flow.py command line option --flatten_names command line option, [1], [2] --flow_config run_fpga_flow.py command line option --format command line option --fpga_fix_pins command line option --fpga_io_map command line option --frame_view command line option, [1] --from_file command line option --generate_random_fabric_key command line option --group_config_block command line option --group_tile command line option --gsb_names command line option --hdl_dir command line option --help command line option, [1], [2] --hierarchical command line option --ignore_global_nets_on_pins command line option --include_module_keys command line option --include_signal_init command line option, [1] --include_timing command line option --input command line option --instance_name command line option --interactive command line option --io_naming command line option --K run_fpga_flow.py command line option --keep_dont_care_bits command line option --load_fabric_key command line option --max_delay command line option --max_route_width_retry run_fpga_flow.py command line option --maxthreads command line option --min_delay command line option --min_route_chan_width run_fpga_flow.py command line option --name_module_using_index command line option --no_time_stamp command line option, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11] --output command line option, [1] --output_hierarchy command line option --pcf command line option

--pin_constraints_file command line option, [1], [2], [3], [4] --pin_table command line option --pin_table_direction_convention command line option --power run_fpga_flow.py command line option --power_tech run_fpga_flow.py command line option --print_user_defined_template command line option --read_file command line option --reference command line option --reference_benchmark_file_path command line option, [1], [2] --reference_fabricA_names command line option --reference_fabricB_names command line option --remove_run_dir command line option --renamed_fabricA_names command line option --report command line option --run_dir run_fpga_flow.py command line option --show_thread_logs command line option --skip_thread_logs command line option --sort_gsb_chan_node_in_edges command line option --test_run command line option --testbench_type command line option --time_unit command line option, [1], [2], [3] --top_module command line option run_fpga_flow.py command line option --unique command line option --use_relative_path command line option, [1], [2], [3] --verbose command line option, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37] --verific run_fpga_flow.py command line option --version command line option --write_fabric_key command line option --write_file command line option --yosys_tmpl run_fpga_flow.py command line option --ys_rewrite_tmpl run_fpga_flow.py command line option <accuracy command line option <bank command line option, [1] <bench_name>_autocheck_top_tb.v command line option <bench_name>_formal_random_top_tb.v command line option <bench_name>_include_netlist.v command line option <bench_name>_top_formal_verification.v command line option <circuit_model command line option <clock command line option, [1] <design command line option <design_technology command line option, [1], [2], [3], [4] <device_model command line option <device_technology command line option <input_buffer command line option <interconnect command line option <key command line option <lib command line option <logical_tile_name>.v command line option <lut_input_buffer command line option <lut_input_inverter command line option <lut_intermediate_buffer command line option <mode command line option <module command line option <monte_carlo command line option <operating command line option <operating_condition command line option <output_buffer command line option <output_log command line option <pass_gate_logic command line option <pb_type command line option, [1] <physical_tile_name>.v command line option <pmos|nmos command line option <port command line option, [1], [2], [3], [4] <programming command line option <region command line option <rise|fall command line option, [1] <rram command line option <runtime command line option <tile command line option <variation command line option <wire_param command line option

A

arch<arch_label> command line option

B

bench<bench_label> command line option bench<bench_label>_act command line option bench<bench_label>_chan_width command line option bench<bench_label>_read_verilog_options command line option bench<bench_label>_top command line option bench<bench_label>_verific_include_dir command line option bench<bench_label>_verific_library_dir command line option bench<bench_label>_verific_read_lib_name<lib_label> command line option bench<bench_label>_verific_read_lib_src<lib_label> command line option bench<bench_label>_verific_search_lib command line option bench<bench_label>_verific_systemverilog_standard command line option bench<bench_label>_verific_verilog_standard command line option bench<bench_label>_verific_vhdl_standard command line option bench<bench_label>_verilog command line option bench<bench_label>_yosys command line option

bench<bench_label>_yosys_args command line option bench<bench_label>_yosys_blackbox_modules command line option bench<bench_label>_yosys_bram_map_rules command line option bench<bench_label>_yosys_bram_map_verilog command line option bench<bench_label>_yosys_cell_sim_systemverilog command line option bench<bench_label>_yosys_cell_sim_verilog command line option bench<bench_label>_yosys_cell_sim_vhdl command line option bench<bench_label>_yosys_dff_map_verilog command line option bench<bench_label>_yosys_dsp_map_parameters command line option bench<bench_label>_yosys_dsp_map_verilog command line option big_endian command line option bitstream_offset command line option Build command line option BUILD_TYPE command line option

C

cbx_<x>_<y>.v command line option cby_<x>_<y>.v command line option ccff_head_indices command line option circuit_model_name command line option, [1] clear-task-run command line option CMAKE_FLAGS command line option CMAKE_GOALS command line option command line option --activity_file --batch_execution --batch_mode --bitstream --blif --bus_group_file, [1], [2], [3] --command --command_stream --compress_routing --constrain_cb --constrain_configurable_memory_outputs --constrain_global_port --constrain_grid --constrain_non_clock_global_port --constrain_routing_multiplexer_outputs --constrain_sb --constrain_switch_block_outputs --constrain_zero_delay_paths --debug, [1] --default_net_type, [1], [2], [3], [4] --depth, [1] --design_constraints --duplicate_grid_pin --dut_module, [1] --embed_bitstream --exclude --exclude_rr_info --exit_on_fail --explicit_port_mapping, [1], [2], [3], [4] --fabric_netlist_file_path, [1], [2] --fast_configuration, [1] --file, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27] --fix --flatten_names, [1], [2] --format --fpga_fix_pins --fpga_io_map --frame_view, [1] --from_file --generate_random_fabric_key --group_config_block --group_tile --gsb_names --hdl_dir --help, [1], [2] --hierarchical --ignore_global_nets_on_pins --include_module_keys --include_signal_init, [1] --include_timing --input --instance_name --interactive --io_naming --keep_dont_care_bits --load_fabric_key --max_delay --maxthreads --min_delay --name_module_using_index --no_time_stamp, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11] --output, [1] --output_hierarchy --pcf --pin_constraints_file, [1], [2], [3], [4] --pin_table --pin_table_direction_convention --print_user_defined_template --read_file --reference --reference_benchmark_file_path, [1], [2] --reference_fabricA_names --reference_fabricB_names --remove_run_dir --renamed_fabricA_names --report --show_thread_logs --skip_thread_logs --sort_gsb_chan_node_in_edges --test_run --testbench_type --time_unit, [1], [2], [3] --top_module --unique --use_relative_path, [1], [2], [3] --verbose, [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37] --version --write_fabric_key --write_file <accuracy <bank, [1] <bench_name>_autocheck_top_tb.v <bench_name>_formal_random_top_tb.v <bench_name>_include_netlist.v <bench_name>_top_formal_verification.v <circuit_model <clock, [1] <design <design_technology, [1], [2], [3], [4] <device_model <device_technology <input_buffer <interconnect <key <lib <logical_tile_name>.v <lut_input_buffer <lut_input_inverter <lut_intermediate_buffer <mode <module <monte_carlo <operating <operating_condition <output_buffer <output_log <pass_gate_logic <pb_type, [1] <physical_tile_name>.v <pmos|nmos <port, [1], [2], [3], [4] <programming <region <rise|fall, [1] <rram <runtime <tile <variation <wire_param arch<arch_label> bench<bench_label> bench<bench_label>_act bench<bench_label>_chan_width bench<bench_label>_read_verilog_options bench<bench_label>_top bench<bench_label>_verific_include_dir bench<bench_label>_verific_library_dir bench<bench_label>_verific_read_lib_name<lib_label> bench<bench_label>_verific_read_lib_src<lib_label> bench<bench_label>_verific_search_lib bench<bench_label>_verific_systemverilog_standard bench<bench_label>_verific_verilog_standard bench<bench_label>_verific_vhdl_standard bench<bench_label>_verilog bench<bench_label>_yosys bench<bench_label>_yosys_args bench<bench_label>_yosys_blackbox_modules bench<bench_label>_yosys_bram_map_rules bench<bench_label>_yosys_bram_map_verilog bench<bench_label>_yosys_cell_sim_systemverilog bench<bench_label>_yosys_cell_sim_verilog bench<bench_label>_yosys_cell_sim_vhdl bench<bench_label>_yosys_dff_map_verilog bench<bench_label>_yosys_dsp_map_parameters bench<bench_label>_yosys_dsp_map_verilog big_endian bitstream_offset Build BUILD_TYPE cbx_<x>_<y>.v cby_<x>_<y>.v ccff_head_indices circuit_model_name, [1] clear-task-run CMAKE_FLAGS CMAKE_GOALS Comments content Continued core_name create-task default default_path default_segment default_switch default_val default_value dir direction end_x end_y fabric_netlists.v fpga_defines.v fpga_flow fpga_top.v frame_based, [1] Functional General-purpose, [1], [2] ghcr.io/lnis-uofu/openfpga-master:latest given Global, [1] goto_task GPIO_type id, [1] interconnection_type inv_buf_passgate.v is_config_enable is_dummy is_global is_mode_select_bitstream list-tasks local_encoder.v luts.v mapped_pin memories.v memory_bank, [1] muxes.v name, [1], [2], [3], [4], [5], [6], [7] net, [1], [2] num_banks num_regions number_of_bits, [1] orientation pad pb_type physical_mode_pin_initial_offset physical_mode_pin_rotate_offset physical_mode_port_rotate_offset physical_pb_type_index_factor pin, [1] port port_name power_analysis power_tech_file protocol ql_memory_bank, [1], [2] run-modelsim run-regression-local run-task sb_<x>_<y>.v scan_chain set_io shrink_boundary source spice_netlist spice_output start_x start_y style sub_Fs sub_type tap through_channel tile_<x>__<y>_.v tile_pin tileable timeout_each_job top_name type, [1] unset-openfpga user_defined_templates.v vanilla verific verilog_output width wires.v x, [1] x_dir y, [1] y_dir z

Comments command line option content command line option Continued command line option core_name command line option create-task command line option

D

default command line option default_path command line option default_segment command line option default_switch command line option

default_val command line option default_value command line option dir command line option direction command line option

E

end_x command line option

end_y command line option

F

fabric_netlists.v command line option fpga_defines.v command line option fpga_flow command line option

fpga_top.v command line option frame_based command line option, [1] Functional command line option

G

General-purpose command line option, [1], [2] ghcr.io/lnis-uofu/openfpga-master:latest command line option given command line option

Global command line option, [1] goto_task command line option GPIO_type command line option

I

id command line option, [1] interconnection_type command line option inv_buf_passgate.v command line option is_config_enable command line option

is_dummy command line option is_global command line option is_mode_select_bitstream command line option

L

list-tasks command line option local_encoder.v command line option

luts.v command line option

M

mapped_pin command line option memories.v command line option

memory_bank command line option, [1] muxes.v command line option

N

name command line option, [1], [2], [3], [4], [5], [6], [7] net command line option, [1], [2] num_banks command line option

num_regions command line option number_of_bits command line option, [1]

O

orientation command line option

P

pad command line option pb_type command line option physical_mode_pin_initial_offset command line option physical_mode_pin_rotate_offset command line option physical_mode_port_rotate_offset command line option physical_pb_type_index_factor command line option

pin command line option, [1] port command line option port_name command line option power_analysis command line option power_tech_file command line option protocol command line option

Q

ql_memory_bank command line option, [1], [2]

R

run-modelsim command line option run-regression-local command line option run-task command line option run_fpga_flow.py command line option --activity_file --base_verilog --black_box_ace --debug --fix_route_chan_width --flow_config --K --max_route_width_retry --min_route_chan_width --power --power_tech --run_dir --top_module --verific --yosys_tmpl --ys_rewrite_tmpl

S

sb_<x>_<y>.v command line option scan_chain command line option set_io command line option shrink_boundary command line option source command line option spice_netlist command line option

spice_output command line option start_x command line option start_y command line option style command line option sub_Fs command line option sub_type command line option

T

tap command line option through_channel command line option tile_<x>__<y>_.v command line option tile_pin command line option

tileable command line option timeout_each_job command line option top_name command line option type command line option, [1]

U

unset-openfpga command line option

user_defined_templates.v command line option

V

vanilla command line option verific command line option

verilog_output command line option

W

width command line option

wires.v command line option

X

x command line option, [1]

x_dir command line option

Y

y command line option, [1]

y_dir command line option

Z

z command line option